The present invention relates to a flag control circuit which is contained in a central processing unit (CPU) in a single chip microcomputer to control a flag.
In general, such a single chip microprocessor comprises an arithmetic and logic unit (ALU) included in a central processing unit operated in accordance with a microprogram. The ALU carries out an arithmetic and logic operation in connection with a pair of data signals each of which is composed of a predetermined number of bits, for example, sixteen (16) bits. The predetermined number of bits may be referred to as a predetermined bit length.
It often happens that the ALU should process a data signal which is longer than the predetermined bit length and which may have a bit length of, for example, twenty-four (24) bits. In this event, the ALU usually executes a calculation by dividing the bit length of the data signal into a lower digit part of, for example, sixteen bits and a higher digit part of, for example, eight (8) bits.
Under the circumstances, it is necessary to monitor specific states, for example, null states in the lower and the higher digit parts so as to decide a branch point in a sequencer operated by the microprogram. To this end, a flag which may be called a zero flag is produced under control of the microprogram to specify the null states which occur in the lower and the higher digit parts. The zero flag may take a predetermined logic level, for example, a logic "1" level.
More specifically, a calculation for the lower digit part is executed to produce a first zero flag signal when the lower digit part is representative of the null state. The first zero flag signal is then supplied to the sequencer which decides a first branch point in the microprogram with reference to the first zero flag signal.
Thereafter, another calculation for the higher digit part is executed to produce a second zero flag signal when the higher digit part is representative of a null state. The second zero flag signal is also supplied to the sequencer. The sequencer decides a next branch point in the microprogram with reference to the second zero flag signal.
A final branch point is determined after production of the first and the second zero flag signals.
Thus, according to the above-mentioned conventional flag control, a state of a zero flag must be checked so as to decide the branch point in accordance with the microprogram which may be considered as software.
Such use of software or firmware makes a microprogram control complicated, since steps are inevitably increased in number in the microprogram. This results in an increase of clocks and undesirably lengthens a calculation of the bit length of the above-mentioned 24 bits. In other words, it is difficult to obtain the final zero flag in a short time, when the above-described calculation over the bit length of 24 bits is executed.